Instruction cache aging mitigation through Instruction Set Encoding

Anteneh Gebregiorgis, Fabian Oboril, Mehdi B. Tahoori, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

Abstract

The reliability of embedded processors fabricated using nanoscale technology nodes is threatened by accelerated transistor aging particularly, Bias Temperature Instability (BTI). In embedded memories such as instruction caches, BTI degrades the Static Noise Margin (SNM) of the memory cell, which in turn affects the stability of the stored value. Various bit flipping based solutions have been proposed to address BTI-induced aging of memory components. Nevertheless, the state-of-the-art techniques have considerable area and power overheads. In this paper, we propose an aging-aware instruction encoding technique to mitigate BTI-induced aging of instruction caches. Opcode, register and function code fields of an instruction are re-encoded so that the BTI-induced aging of the instruction cache is minimized. Simulation results show that the proposed technique achieves up to 40% SNM degradation improvement (equivalent to 47% MTTF improvement) with a negligible power overhead (0.1%).
Original languageEnglish
Title of host publicationProceedings of the 17th International Symposium on Quality Electronic Design, ISQED 2016
EditorsPeter Wright, Saibal Mukhopadhyay, Brian Cline
Place of PublicationPiscataway, NJ
PublisherIEEE
Pages325-330
Number of pages6
ISBN (Print)978-1-5090-1213-8
DOIs
Publication statusPublished - 2016
Event17th International Symposium on Quality Electronic Design, ISQED 2016 - Santa Clara, CA, United States
Duration: 14 Mar 201616 Mar 2016

Conference

Conference17th International Symposium on Quality Electronic Design, ISQED 2016
Abbreviated titleISQED 2016
CountryUnited States
CitySanta Clara, CA
Period14/03/1616/03/16

Keywords

  • Static Noise Margin
  • Transistor Aging
  • BTI
  • SRAM

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