Interconnect Networks for Resistive Computing Architectures

Hoang Anh Du Nguyen, Lei Xie, Jintao Yu, Mottaqiallah Taouil, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

1 Citation (Scopus)

Abstract

Today's computing systems suffer from a memory/communication bottleneck, resulting in high energy consumption and saturated performance. This makes them inefficient in solving data-intensive applications at reasonable cost. Computation-In-Memory (CIM) architecture, based on the integration of storage and computation in the same physical location using non-volatile memristor crossbar technology, offers a potential solution to the memory bottleneck. An efficient interconnect network is essential to maximize CIM's architectural performance. This paper presents three interconnect network schemes for CIM architecture; these are (1) CMOS-based, (2) memristor-based and (3) hybrid cmos/memristor interconnect network scheme. To illustrate the feasibility of such schemes, a CIM parallel adder is used as a case study. The results show that the hybrid interconnect network scheme achieves a higher performance in comparison with the CMOS-based and memristor-based interconnect scheme in terms of delay, energy and area.
Original languageEnglish
Title of host publication2017 12th International Conference on Design &Technology of Integrated Systems in Nanoscale Era (DTIS)
Place of PublicationDanvers
PublisherIEEE
Pages1-6
Number of pages6
ISBN (Electronic)978-1-5090-6377-2
ISBN (Print)978-1-5090-6378-9
DOIs
Publication statusPublished - 2017
Event2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS) - Palma de Mallorca, Spain
Duration: 4 Apr 20176 Apr 2017

Conference

Conference2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)
Abbreviated titleDTIS 2017
CountrySpain
CityPalma de Mallorca
Period4/04/176/04/17

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