Time-division Multiplexing Automata Processor

Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui

Research output: Chapter in Book/Conference proceedings/Edited volumeConference contributionScientificpeer-review

2 Citations (Scopus)
197 Downloads (Pure)


Automata Processor (AP) is a special implementation of non-deterministic finite automata that performs pattern matching by exploring parallel state transitions. The implementation typically contains a hierarchical switching network, causing long latency. This paper proposes a methodology to split such a hierarchical switching network into multiple pipelined stages, making it possible to process several input sequences in parallel by using time-division multiplexing. We use a new resistive RAM based AP (instead of known DRAM or SRAM based) to illustrate the potential of our method. The experimental results show that our approach increases the throughput by almost a factor of 2 at a cost of marginal area overhead.
Original languageEnglish
Title of host publication2019 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Subtitle of host publicationProceedings
Number of pages6
ISBN (Electronic)978-3-98192632-3
ISBN (Print)978-1-7281-0331-0
Publication statusPublished - 2019
EventDATE 2019 : Design, Automation and Test in Europe Conference and Exhibition - Florence, Italy
Duration: 25 Mar 201929 Mar 2019
Conference number: 22nd


ConferenceDATE 2019


  • automata
  • parallel processing
  • time-devision multiplexing


Dive into the research topics of 'Time-division Multiplexing Automata Processor'. Together they form a unique fingerprint.

Cite this