Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

Shayesteh Masoumian; Roel  Maes; Rui Wang; Karthik Keni  Yerriswamy; Geert-Jan Schrijen; Said Hamdioui; Mottaqiallah Taouil

doi:10.1109/VLSI-SoC57769.2023.10321895

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

Shayesteh Masoumian, Roel Maes, Rui Wang, Karthik Keni Yerriswamy, Geert-Jan Schrijen , Said Hamdioui, Mottaqiallah Taouil

Computer Engineering

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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Abstract

SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.

Original language	English
Title of host publication	Proceedings of the 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)
Publisher	IEEE
Number of pages	6
ISBN (Electronic)	979-8-3503-2599-7
ISBN (Print)	979-8-3503-2600-0
DOIs	https://doi.org/10.1109/VLSI-SoC57769.2023.10321895
Publication status	Published - 2023
Event	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC) - Dubai, United Arab Emirates Duration: 16 Oct 2023 → 18 Oct 2023 Conference number: 31st

Conference

Conference	2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)
Country/Territory	United Arab Emirates
City	Dubai
Period	16/10/23 → 18/10/23

Bibliographical note

Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care
Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.

Keywords

Bias
FinFET
Power Supply Network
SRAM PUF
Temperature

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Modeling_and_Analysis_of_SRAM_PUF_Bias_Patterns_in_14nm_and_7nm_FinFET_Technology_NodesFinal published version, 1.73 MB

Cite this

@inproceedings{ce904b003c4d4ddc8857361a078d1956,

title = "Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes",

abstract = "SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.",

keywords = "Bias, FinFET, Power Supply Network, SRAM PUF, Temperature",

author = "Shayesteh Masoumian and Roel Maes and Rui Wang and Yerriswamy, {Karthik Keni} and Geert-Jan Schrijen and Said Hamdioui and Mottaqiallah Taouil",

note = "Green Open Access added to TU Delft Institutional Repository 'You share, we take care!' - Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.; 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC) ; Conference date: 16-10-2023 Through 18-10-2023",

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doi = "10.1109/VLSI-SoC57769.2023.10321895",

language = "English",

isbn = "979-8-3503-2600-0",

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Masoumian, S, Maes, R, Wang, R, Yerriswamy, KK, Schrijen , G-J, Hamdioui, S & Taouil, M 2023, Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. in Proceedings of the 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC), Dubai, United Arab Emirates, 16/10/23. https://doi.org/10.1109/VLSI-SoC57769.2023.10321895

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes. / Masoumian, Shayesteh; Maes, Roel ; Wang, Rui et al.
Proceedings of the 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC). IEEE, 2023.

Research output: Chapter in Book/Conference proceedings/Edited volume › Conference contribution › Scientific › peer-review

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T1 - Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

AU - Masoumian, Shayesteh

AU - Maes, Roel

AU - Wang, Rui

AU - Yerriswamy, Karthik Keni

AU - Schrijen , Geert-Jan

AU - Hamdioui, Said

AU - Taouil, Mottaqiallah

N1 - Conference code: 31st

PY - 2023

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N2 - SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.

AB - SRAM Physical Unclonable Functions (PUFs) are one of the popular forms of PUFs that can be used to generate unique identifiers and randomness for security purposes. Hence, their resilience to attacks is crucial. The probability of attacks increases when the SRAM PUF start-up values follow a predictable pattern which we refer to as bias. In this paper, we investigate the parameters impacting the SRAM PUF bias of advanced FinFET SRAM designs. In particular, we analyze the bias with respect to temperature, mismatches in the power supply network, and ramp-up time. We also consider process variation, circuit noise, and SRAM layout in our analysis. Our simulations results match with the silicon measurements. From the experiments we conclude that (i) the SRAM layout and in particular the power supply network can lead to a bias, (ii) this bias increases with temperature, and (iii) this bias increases when the supply ramp-up time decreases.

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KW - FinFET

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M3 - Conference contribution

SN - 979-8-3503-2600-0

BT - Proceedings of the 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)

PB - IEEE

T2 - 2023 IFIP/IEEE 31st International Conference on Very Large Scale Integration (VLSI-SoC)

Y2 - 16 October 2023 through 18 October 2023

ER -

Modeling and Analysis of SRAM PUF Bias Patterns in 14nm and 7nm FinFET Technology Nodes

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Keywords

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