Resistive Random Access Memory (RRAM, or ReRAM) is a promising memory technology to replace Flash because of its low power consumption, high storage density, and simple integration in existing IC production processes. This has motivated many companies to invest in this technology. However, RRAM manufacturing introduces new failure mechanisms and faults that cause functional errors. These faults cannot all be detected by state-of-the-art test and diagnosis solutions, thus leading to slower product development and low-quality products. This paper introduces a design-for-test (DFT) based on a parallel-multi-reference read (PMRR) circuit that can detect all RRAM array faults. The PMRR circuit replaces the standard sense amplifier and compares the cell’s state to multiple references during one read operation. Thus, it can be used as a DFT scheme and a normal read circuit at once. This allows for speeding up production testing and the online detection of faults. Furthermore, the circuit is extendable so that more references can be compared, which is required for efficient diagnosis. Finally, the references can be adjusted to maximize the production yield. The circuit outperforms state-of-the-art solutions because it can detect all RRAM faults during diagnosis, production testing, and during its application in the field while minimizing yield loss.
|Title of host publication||Proceedings of the 2023 IEEE European Test Symposium (ETS)|
|Number of pages||6|
|Publication status||Published - 2023|
|Event||2023 IEEE European Test Symposium (ETS) - Venezia, Italy|
Duration: 22 May 2023 → 26 May 2023
|Name||Proceedings of the European Test Workshop|
|Conference||2023 IEEE European Test Symposium (ETS)|
|Period||22/05/23 → 26/05/23|
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