TY - GEN
T1 - Device-Aware Test for Back-Hopping Defects in STT-MRAMs
AU - Yuan, Sicong
AU - Taouil, Mottaqiallah
AU - Fieback, Moritz
AU - Xun, Hanzhi
AU - Marinissen, Erik Jan
AU - Kar, Gouri Sankar
AU - Rao, Sidharth
AU - Couet, Sebastien
AU - Hamdioui, Said
N1 - Green Open Access added to TU Delft Institutional Repository ‘You share, we take care!’ – Taverne project https://www.openaccess.nl/en/you-share-we-take-care Otherwise as indicated in the copyright section: the publisher is the copyright holder of this work and the author uses the Dutch legislation to make this work public.
PY - 2023
Y1 - 2023
N2 - The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modelled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms; the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations; new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, dedicated march test and a Design-for-Test solutions are proposed.
AB - The development of Spin-transfer torque magnetic RAM (STT-MRAM) mass production requires high-quality dedicated test solutions, for which understanding and modeling of manufacturing defects of the magnetic tunnel junction (MTJ) is crucial. This paper introduces and characterizes a new defect called Back-Hopping (BH); it also provides its fault models and test solutions. The BH defect causes MTJ state to oscillate during write operations, leading to write failures. The characterization of the defect is carried out based on manufactured MTJ devices. Due to the observed non-linear characteristics, the BH defect cannot be modelled with a linear resistance. Hence, device-aware defect modeling is applied by considering the intrinsic physical mechanisms; the model is then calibrated based on measurement data. Thereafter, the fault modeling and analysis is performed based on circuit-level simulations; new fault primitives/models are derived. These accurately describe the way the STT-MRAM behaves in the presence of BH defect. Finally, dedicated march test and a Design-for-Test solutions are proposed.
UR - http://www.scopus.com/inward/record.url?scp=85162626162&partnerID=8YFLogxK
U2 - 10.23919/DATE56975.2023.10137071
DO - 10.23919/DATE56975.2023.10137071
M3 - Conference contribution
AN - SCOPUS:85162626162
T3 - Proceedings -Design, Automation and Test in Europe, DATE
BT - 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023 - Proceedings
PB - Institute of Electrical and Electronics Engineers (IEEE)
T2 - 2023 Design, Automation and Test in Europe Conference and Exhibition, DATE 2023
Y2 - 17 April 2023 through 19 April 2023
ER -